![AMD EPYC Milan [Zen 3] chips are 20% faster than EPYC Rome [Zen 2]](https://umtale-media.s3.eu-central-1.amazonaws.com/images/content/873ea69e-22ab-4403-b1e7-7a4fd200f3d8.webp)
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AMD EPYC Milan [Zen 3] chips are 20% faster than EPYC Rome [Zen 2]
Internal AMD data suggests EPYC Milan processors, based on Zen 3, are 20% faster than Zen 2-powered EPYC Rome chips at the same clock speed. However, these are still just rumors.
According to slides from AMD for internal use (demonstrating performance gains within the company), AMD EPYC Milan processors, built on the new Zen 3 architecture, are poised to deliver a 20% advantage over current Zen 2-based EPYC Rome chips, all while running at the same frequency.
Reliable tech publication Hardwareluxx was the source of this information. However, it's still just a rumor, so take these claims with a grain of salt.
CPU codename | Naples | Rome | Milan | Genoa |
Socket | SP3 | SP3 | SP3 | SP5 |
Core count/Architecture | 32x Zen | 64x Zen 2 | 64x Zen 3 | >64x Zen 4 |
CCD / L3 Cache | 8 cores per CCD 2x 16 MB L3-Cache | 8 cores per CCD 2x 16 MB L3-Cache | 8 cores per CCD 1x 32 MB L3-Cache | - |
Process technology | 14 nm | 7 nm | 7 nm | 5 nm |
RAM support | DDR4 | DDR4 | DDR4 | DDR5 |
PCIe version | PCIe 3.0 | PCIe 4.0 | PCIe 4.0 | PCIe 5.0 |
TDP | 120 - 180 W | 120 - 225 W | 120 - 225 W | 120 - 240 W |
The report indicates AMD's Zen 3 architecture should deliver a 15% IPC uplift. However, AMD seems to be taking a differentiated approach with EPYC Milan processors. For instance, 64-core SKUs might see a 15% performance boost, while 32-core variants could gain a more substantial 20% over their current-generation equivalents.
⤢ ВІДКРИТИFurthermore, while earlier each of the two CCXs featured its own 16MB L3 cache, it will now become unified, expanding to 32MB. (Essentially, the cache size per CCD won't change, but it will be faster and more accessible). This alteration should significantly impact overall CPU performance, as cores will no longer need to retrieve data from another CCX's cache.
