Used in: Quadro P5000 Mobile, Quadro P5000 X2 Mobile.
RELEASEMay 27, 2016
FOUNDRYTSMC
PROCESS16 nm
ARCHITECTUREPascal
ROPs64
TMUs128
SPs2,048CUDA
VRAM16GBGDDR5X / GDDR5
TDP200W
DIE FLOORPLANSCHEMATIC · NOT TO SCALE
N17E-Q5-A1 · 16 nm
area 314 mm²
GPC / SM
5 / 16
CUDA
2 048
L2 cache
2 MB
Memory controller
8 × 32-bit
Media engine
NVENC · NVDEC · PureVideo HD
SECTIONShover or click a block
General
13
Identity
ManufacturerNVIDIA
ArchitecturePascal
NameN17E-Q5-A1
CodenameNV134
Package
PackageFCBGA-2152
Package size37.5 mm × 37.5 mm
Die protectionBare Die
Silicon
FoundryTSMC
Process node16 nm
Process typeFinFET
Transistors7,200M
Density22.9M/mm²
Die size314mm²
Configuration
13
Compute blocks
Compute units (SM/CU)16
GPCs / Shader engines5
TPCs / WGPs20
Execution units (FP32)2,048CUDA
TMUs128
ROPs64
Power
Max TDP200W
Specialised units
FP16 units20
FP64 units80
INT32 units2,560
SFUs640
Cache
L1 cache / Shared Memory per SM51KB
L2 cache2,048KB
Memory
03
Max VRAM16GBQuadro P5000
Max memory bus256bit
VRAM typeGDDR5XGDDR5
Clock speeds
03
Base clock1,164MHz
Boost clock1,506MHz
Memory clock1,500MHz
APIs
11
CUDA
6.1 (12.9)
✓Full
Vulkan
1.4
✓Full
OpenCL
3.0
✓Full
OpenGL
4.6
✓Full
DirectXFeature Level 12_1 (DirectX 12)
12.1
✓Full
Shader Model
6.8
✓Full
WDDMDESCRIPTIONWindows Display Driver Model — the Windows display driver model version
3.2
✓Full
VDPAUDESCRIPTIONVideo Decode and Presentation API for Unix — hardware decode feature set
Feature Set H
✓Full
DirectComputeDESCRIPTIONDirect3D compute shaders; the version is the compute shader model
5.0
✓Full
NVIDIA OptiXDESCRIPTIONNVIDIA ray-tracing API; the version is the newest OptiX SDK the chip supports
9.0
✓Full
DirectMLDESCRIPTIONMicrosoft machine-learning API on top of DirectX 12; runs on any DirectX 12 GPU
—
SUPPORT LEVEL✓ Full◐ Partial✕ None
Instructions
09
IDP4ADESCRIPTION8-bit Integer Dot Product and Accumulate into 32 bits (PTX dp4a). From sm_61.
✓Full
IDP2ADESCRIPTION16-bit by 8-bit Integer Dot Product and Accumulate (PTX dp2a). From sm_61.
✓Full
FFMADESCRIPTIONSingle-Precision Fused Multiply-Add. From sm_20; sm_1x only had an unfused MAD.
✓Full
HFMA2DESCRIPTIONPacked fused multiply-add of two FP16 (or BF16) values per instruction (PTX fma.f16x2 / fma.bf16x2). FP16 from sm_53, BF16 from sm_80.FP16 (f16x2) only; packed BF16 (bf16x2) arrived with sm_80.
◐Partial
DFMADESCRIPTIONDouble-Precision Fused Multiply-Add. From sm_13; throughput depends on the number of FP64 units.
✓Full
LOP3.LUTDESCRIPTIONArbitrary three-input bitwise logic function from a truth table (Three-Input Bitwise Logic Operation). From sm_50.
✓Full
SHFLDESCRIPTIONExchanges registers between warp threads without shared memory (Warp Shuffle). From sm_30.
✓Full
ATOMG / ATOMSDESCRIPTIONHardware atomics on global (ATOMG) and shared (ATOMS) memory (PTX atom). Global from sm_11, shared from sm_12.
✓Full
MUFUDESCRIPTIONSpecial functions on the SFUs: sin, cos, ex2, lg2, rcp, rsqrt (Multi-Function Unit). On every CUDA architecture.
✓Full
SUPPORT LEVEL✓ Full◐ Partial✕ None
AI / Compute
21
CUDA
✓Full
Vulkan
✓Full
OpenCL
✓Full
Floating-point formats
FP64◐Stream processors only
FP32◐Stream processors only
TF32✕None
FP16◐Stream processors only
BF16✕None
FP8✕None
MXFP8✕None
MXFP6✕None
FP4✕None
MXFP4✕None
NVFP4✕None
Integer formats
INT32◐Stream processors only
INT16◐Stream processors only
INT8◐Stream processors only
INT4✕None
INT2✕None
INT1✕None
Other
Async DMA / TMA✓ Yes
SUPPORT LEVEL✓ Full◐ Partial✕ None
Theoretical performance
04
FP16 (half)128.6TFLOPS
FP32 (single)8.23TFLOPS
FP64 (double)257.1TFLOPS1:32
Tensor formats
With sparsity✕ No
Media
04
NVENCDESCRIPTIONHardware video encoder
6th Gen
NVDECDESCRIPTIONHardware video decoder
3rd Gen
PureVideo HDDESCRIPTIONNVIDIA hardware video decode feature set
VP8
AV1✕ No
Imagery
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