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NVIDIA GP102 GP102-400-A1

Used in: TITAN X Pascal.

RELEASEAugust 2, 2016
FOUNDRYTSMC
PROCESS16 nm
ARCHITECTUREPascal
ROPs96
TMUs224
SPs3,584CUDA
VRAM12GBGDDR5X / GDDR5
TDP250W
DIE FLOORPLANSCHEMATIC · NOT TO SCALE
GP102-400-A1 · 16 nm
area 471 mm²
GigaThread Engine · Front-endGigaThread EngineNVENC · 6th Gen · Media engineNVENC6th GenNVDEC · 3rd Gen · VP8 · Media engineNVDEC3rd Gen · VP8Memory controller 0 · 32-bit GDDR5X / GDDR5MC32bMemory controller 1 · 32-bit GDDR5X / GDDR5MC32bMemory controller 2 · 32-bit GDDR5X / GDDR5MC32bMemory controller 3 · 32-bit GDDR5X / GDDR5MC32bMemory controller 4 · 32-bit GDDR5X / GDDR5MC32bMemory controller 5 · 32-bit GDDR5X / GDDR5MC32bMemory controller 6 · 32-bit GDDR5X / GDDR5MC32bMemory controller 7 · 32-bit GDDR5X / GDDR5MC32bMemory controller 8 · 32-bit GDDR5X / GDDR5MC32bMemory controller 9 · 32-bit GDDR5X / GDDR5MC32bMemory controller 10 · 32-bit GDDR5X / GDDR5MC32bMemory controller 11 · 32-bit GDDR5X / GDDR5MC32bGPC 0 · 4 SM · 512 CUDA · 1 fused offGPC 0GPC 1 · 4 SM · 512 CUDA · 1 fused offGPC 1GPC 2 · 5 SM · 640 CUDAGPC 2GPC 3 · 5 SM · 640 CUDAGPC 3GPC 4 · 5 SM · 640 CUDAGPC 4GPC 5 · 5 SM · 640 CUDAGPC 5L2 cache · 3 MBL2 cacheL2 cache · 3 MB3 MBPCIePCIeMemory interface · 384-bit · GDDR5X / GDDR5 · 12 GB384-bitGDDR5X / GDDR5 · 12 GB
GPC / SM
6 / 28 · 2 fused off
CUDA
3 584
L2 cache
3 MB
Memory controller
12 × 32-bit
Media engine
NVENC · NVDEC
SECTIONSclick a block or section

General

12

Identity

ManufacturerNVIDIA
ArchitecturePascal
NameGP102-400-A1
CodenameNV132

Package

PackageFCBGA-2397
Package size45 mm × 45 mm

Silicon

FoundryTSMC
Process node16 nm
Process type16FF+ FinFET
Transistors11,800M
Density25.1M/mm²
Die size471mm²

Configuration

12

Compute blocks

Compute units (SM/CU)28
GPCs / Shader engines6
TPCs / WGPs30
Execution units (FP32)3,584CUDA
TMUs224
ROPs96

Power

Max TDP250W

Specialised units

FP16 units0
FP64 units120
SFUs956

Cache

L1 cache / Shared Memory per SM48KB
L2 cache3,072KB

Memory

03
Max VRAM12GB
Max memory bus384bit
VRAM typeGDDR5XGDDR5

Clock speeds

03
Base clock1,417MHz
Boost clock1,531MHz
Memory clock1,251MHz

APIs

11
CUDA
6.1
Full
Vulkan
1.4
Full
OpenCL
3.0
Full
OpenGL
4.6
Full
DirectXFeature Level 12_1 (DirectX 12)
12.1
Full
Shader Model
6.8
Full
WDDMDESCRIPTIONWindows Display Driver Model — the Windows display driver model version
3.2
Full
VDPAUDESCRIPTIONVideo Decode and Presentation API for Unix — hardware decode feature set
Feature Set H
Full
DirectComputeDESCRIPTIONDirect3D compute shaders; the version is the compute shader model
5.0
Full
NVIDIA OptiXDESCRIPTIONNVIDIA ray-tracing API; the version is the newest OptiX SDK the chip supports
9.0
Full
DirectMLDESCRIPTIONMicrosoft machine-learning API on top of DirectX 12; runs on any DirectX 12 GPU
—
Full
SUPPORT LEVEL✓ Full◐ Partial✕ None

Instructions

09
IDP4ADESCRIPTION8-bit Integer Dot Product and Accumulate into 32 bits (PTX dp4a). From sm_61.
Full
IDP2ADESCRIPTION16-bit by 8-bit Integer Dot Product and Accumulate (PTX dp2a). From sm_61.
Full
FFMADESCRIPTIONSingle-Precision Fused Multiply-Add. From sm_20; sm_1x only had an unfused MAD.
Full
HFMA2DESCRIPTIONPacked fused multiply-add of two FP16 (or BF16) values per instruction (PTX fma.f16x2 / fma.bf16x2). FP16 from sm_53, BF16 from sm_80.FP16 (f16x2) only; packed BF16 (bf16x2) arrived with sm_80.
Partial
DFMADESCRIPTIONDouble-Precision Fused Multiply-Add. From sm_13; throughput depends on the number of FP64 units.
Full
LOP3.LUTDESCRIPTIONArbitrary three-input bitwise logic function from a truth table (Three-Input Bitwise Logic Operation). From sm_50.
Full
SHFLDESCRIPTIONExchanges registers between warp threads without shared memory (Warp Shuffle). From sm_30.
Full
ATOMG / ATOMSDESCRIPTIONHardware atomics on global (ATOMG) and shared (ATOMS) memory (PTX atom). Global from sm_11, shared from sm_12.
Full
MUFUDESCRIPTIONSpecial functions on the SFUs: sin, cos, ex2, lg2, rcp, rsqrt (Multi-Function Unit). On every CUDA architecture.
Full
SUPPORT LEVEL✓ Full◐ Partial✕ None

AI / Compute

21
CUDA
Full
Vulkan
Full
OpenCL
Full

Floating-point formats

FP64Stream processors only
FP32Stream processors only
TF32None
FP16Stream processors only
BF16None
FP8None
MXFP8None
MXFP6None
FP4None
MXFP4None
NVFP4None

FP64 (1:32)

FP16 (1:64)

Integer formats

INT32Stream processors only
INT16Stream processors only
INT8Stream processors only
INT4None
INT2None
INT1None

Other

Async DMA / TMA✕ No
SUPPORT LEVEL✓ Full◐ Partial✕ None

Theoretical performance

04
FP16 (half)1:64197.4GFLOPS
FP32 (single)12.63TFLOPS
FP64 (double)1:32395GFLOPS
INT8 (shaders)43.5TOPS

Media

03
NVENCDESCRIPTIONHardware video encoder
6th Gen
NVDECDESCRIPTIONHardware video decoder
3rd Gen
PureVideo HDDESCRIPTIONNVIDIA hardware video decode feature set
VP8
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